1. Field of the Invention
The present invention relates to single crystal silicon wafers for use in the manufacture of insulated gate bipolar transistors, and to a method of manufacturing such single crystal silicon wafers.
Priority is claimed on Japanese Patent Application No. 2006-010756, filed Jan. 19, 2006, the content of which is incorporated herein by reference.
2. Background Art
The insulated gate bipolar transistor (IGBT) is a gate voltage driven switching device suitable for high-power control that is employed, for example, as an inverter in hybrid cars, air conditioning equipment and refrigerators. IGBTs are provided with three electrodes—an emitter, a collector and a gate. A voltage applied to the gate, which has been formed on the top side of the device over an insulating oxide film, controls the current between the emitter on the top side of the device and the collector on the back side.
Because the IGBT is a device that uses a gate insulated with an oxide film to control current, the gate oxide integrity (GOI) is important. If the single crystal silicon wafer contains defects, those defects are taken up into the gate oxide and become a cause of gate oxide breakdown.
IGBTs are not devices which, in the manner of LSI devices such as memory chips, use only the near-surface portion of the wafer in the lateral direction. Rather, being devices which use the wafer in the vertical direction, their characteristics are influenced by the bulk qualities of the wafer. The recombination lifetime and resistivity are particularly important qualities. Given that the recombination lifetime decreases with crystal defects in the substrate, control that keeps crystal defects from arising even when the wafer passes through device forming processes is essential. With regard to resistivity, the qualities desired are uniformity and stability. It is important that the resistivity be uniform not only in the plane of the wafer, but also between wafers, that is, in the length direction of the silicon ingot, and that it remain unchanged even on passing through thermal device processes.
Epitaxial wafers (abbreviated below as “epiwafer”) are used as so-called punch through (PT) type IGBT substrates in which a depletion layer comes into contact with the collector side when the current is off. However, a problem with PT-type IGBTs is their high cost on account of the use of an epiwafer. In addition, due to lifetime control, the switching loss at high temperatures increases. As a result, the on voltage at high temperatures decreases and the current concentrates at specific circuit components during parallel use, which sometimes causes failure.
To resolve the defects of PT-type substrates, non-punch through (NPT) type IGBTs have been developed in which the depletion layer does not come into contact with the collector side when the current is off. Furthermore, recently, so-called field stop (FS) IGBTs are being produced which have a trench gate construction and in which a field stop layer is formed on the collector side. Such FS-IGBTs have a lower ON voltage and little switching loss. Wafers with a diameter of 150 mm or less that have been cut from a silicon single crystal grown by the float zone (FZ) method (referred to below as “FZ wafers”) have hitherto been used as the substrates for NPT and FS-type IGBTs.
Although FZ wafers are less expensive than epiwafers, to further lower the production costs of IGBTs, it is necessary to create larger diameter wafers. However, it is exceedingly difficult to grow single crystals with a diameter of more than 150 mm by the FZ method, and even were such production to be carried out, the stable supply of such single crystals at a low cost would be very difficult to achieve.
We thus attempted to produce single crystal silicon wafers for IGBTs by the Czochralski (CZ) process, which is capable of easily growing large-diameter crystals.
The art disclosed in JP-A 2001-146496, JP-A 2000-7486 and JP-A 2002-29891 described below is all aimed at reducing defects within the wafer. JP-A 2001-146496 discloses a single crystal silicon wafer which has been grown by the CZ method and is either nitrogen doped, composed throughout of N-regions and has an interstitial oxygen concentration of 8 ppm or less, or is nitrogen doped, eliminates throughout at least point defects and dislocation clusters and has an interstitial oxygen concentration of 8 ppm or less.
JP-A 2000-7486 discloses a method for producing a silicon single crystal that is pulled by the Czochralski method while being doped with oxygen and nitrogen. During the pulling operation, the silicon single crystal is doped with oxygen at a concentration below 6.5×1017 atoms/cm3 and with nitrogen at a concentration above 5×1013 atoms/cm3.
JP-A 2002-29891 discloses a silicon semiconductor substrate which is grown by the Czochralski method from a melt to which nitrogen has been added; which has a nitrogen concentration of at least 2×1014 atoms/cm3 but not more than 2×1016 atoms/cm3 and an oxygen concentration of not more than 7×1017 atoms/cm3; which has the various following surface defect densities: flow pattern defects (FPD)≦0.1 defect/cm2, Secco etch pit defects (SEPD)≦0.1 defect/cm2 and oxygen-induced stacking faults (OSF)≦0.1 defect/cm2; which has the following internal defect density: defects detected by IR light scattering tomography (LSTD)≦1×105 defects/cm3; and which has the following gate oxide integrity characteristics: a time-zero dielectric breakdown (TZDB) high C-mode pass rate of ≧90%, and a time-dependent dielectric breakdown (TDDB) pass rate of ≧90%.